Article ID: 000076623 Content Type: Troubleshooting Last Reviewed: 07/15/2020

Why do both rx_clk and tx_clk output of the Intel® FPGA Triple-Speed Ethernet IP core stop after about 1.7 sec in the simulation?

Environment

  • Cyclone® V FPGAs and SoC FPGAs
  • Arria® V FPGAs and SoC FPGAs
  • Stratix® V FPGAs
  • Intel® Quartus® Prime Standard Edition
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    Critical Issue

    Description

    Due to a problem with the simulation model of the Intel® FPGA Triple-Speed Ethernet IP core, both rx_clk and tx_clk output of the Intel® FPGA Triple-Speed Ethernet IP core stop after about 1.7 sec in the simulation.
    This is due to the MSB of the internal 32-bits clock counter not toggled.
    This problem can be seen in only simulation. 

    Resolution

    There is no workaround for this problem.

    This problem is fixed starting with the Intel® Quartus® Prime Standard Edition software version 21.1.

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