Why do I see unconstrained clock warnings when compiling the SerialLite III Streaming Intel® Stratix® 10 FPGA Design Example?

Due to a problem with the SerialLite III Streaming Intel® Stratix® 10 FPGA Design Example in the Intel® Quartus® Prime Pro Edition software version 18.1 and later, an unconstrained clock warning may be observed in timing analysis due to a missing constraint in the jtag_timing_template.sdc file:

Warning(332060): Node: altera_reserved_tck was determined to be a clock but was found without an associated clock assignment

To work around this problem, add the line below at the end of the jtag_timing_template.sdc file:

    set_jtag_timing_constraints

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.