Article ID: 000076621 Content Type: Troubleshooting Last Reviewed: 03/16/2020

Why does the design example of the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps variants have incorrect reference clock pin assignments?

Environment

  • Intel® Stratix® 10 TX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Ethernet
  • 25G Ethernet Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    In the Intel® Quartus® Prime Pro Edition Software version 19.2 or earlier, when creating a design example with the Intel® Stratix® 10 E-Tile Hard IP for Ethernet - 10Gbps and 25Gbps base variants, the default reference clock frequency is established as 322 MHz in the Intellectual Property GUI. However, when the design example is generated, the reference clock frequency (i_clk_ref) is mapped to PIN_AN13 of the Intel® Stratix® 10 TX Signal Integrity Devkit with frequency of 156 MHz. Consequently, design example does not work correctly. 

    Resolution

    To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 19.2 or earlier, change the QSF assignment of reference clock(i_clk_ref) to PIN_AN15 on the Intel® Stratix® 10 TX Signal Integrity Devkit which has a default frequency 322 MHz, or change the reference clock frequency to 156 MHz in the IP GUI. 

    This problem is fixed in the Intel® Quartus® Prime Pro Edition Software version 19.3.

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