This problem affects DDR2 and DDR3, QDR II, and RLDRAM II products.
The hard memory interface fabric in Arria V supports clock
rates up to 267 MHz. The example design provided with the IP is
pll_afi_clk, at 533 MHz. The example design
should be clocked by
The workaround for this issue is to modify the example design
pll_half_afi_clk instead of
as the clock.
This issue will be fixed in a future version.