Why do I see a clock crossing timing failure between mgmt_clk and frame_clk in a simplex transmitter mode JESD204B design example?

For a simplex Transmitter mode JESD204B design example targetting Intel® Arria® 10 devices, you might observe timing violations between mgmt_clk and frame_clk in the Intel® Quartus® Prime Pro Edition Sofware version 17.0 or later. Both of these clock domains are in fact asynchronous to each other and thus it is safe to cut paths between both domains.

To work around this, edit the altera_jesd204_ed_<data_path>.sdc file and add the frame_clk (u_altera_jesd204_ed_qsys_<data_path>|core_pll|core_pll|frame_clk) into the set_clock_groups constraint as follows:

set_clock_groups -asynchronous -group {device_clk \

u_altera_jesd204_ed_qsys_<data_path>|core_pll|core_pll|frame_clk \

u_altera_jesd204_ed_qsys_<data_path>|core_pll|core_pll|link_clk \

...} \

-group {mgmt_clk ...} \

-group {altera_reserved_tck}

This issue is fixed starting from Intel® Quartus® Prime Pro Edition Software version 17.1.