Article ID: 000076585 Content Type: Troubleshooting Last Reviewed: 03/15/2019

Why does the VIP suite CVO II IP have no output when video in and out use the same clock?

Environment

    Intel® Quartus® Prime Pro Edition
    Clocked Video Output II (4K Ready) Intel® FPGA IP
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Critical Issue

Description

Due to a problem with Clocked Video Output (CVO) II IP in Quartus® Prime software version v16.0, the CVO II IP may not generate output if the "Number of pixels in Parallel" has a value larger than 1 and the "Video in and out use the same clock" option is enabled.

Resolution

You can disable the "Video in and out use the same clock" option and manually connect the source clock to is_clk and vid_clk ports.

This problem is fixed starting in Quartus Prime software version 16.1.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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