The Quartus II software release versions 14.1 and 15.0 can erroneously allow MAX 10 device designs to use non-existent connectivity between DPCLK pins and the clock network; specifically, the software could allow connectivity from DPCLK0 to GCLK and from DPCLK2 to GCLK. If you use either of these non-existent paths in your design, the software does not indicate any issues, but produces a non-functional design on the FPGA. Refer to the MAX 10 Clocking and PLL User Guide for allowable DPCLK to GCLK connectivity: https://documentation.altera.com/#/00003866-AA.
There is no workaround. This issue will be fixed in an upcoming software release.