When synthesizing a SystemVerilog design in the Quartus® Prime Pro Edition software, you may see fatal error messages similar to those below:
*** Fatal Error: Segment Violation at (nil)
Module: quartus_syn
Stack Trace:
0x44d235: VeriPortConnect::CreatePortRefs(Instance*, unsigned int, unsigned int, unsigned int*, VeriIdDef*) 0x537 (synth_vrfx2)
0x471d16: VeriInstId::InstantiateModule(VeriIdDef*, Netlist*, Map const*, unsigned int, unsigned int, char const*, Map*) 0x89c (synth_vrfx2)
0x4b7933: VeriModuleInstantiation::ElaborateModuleItemInternal(Map*, Map*) 0x2fa7 (synth_vrfx2)
0x4c1eb8: VeriModule::Elaborate(Map*, Array*, unsigned int) 0xfcc (synth_vrfx2)
0x5594f2: veri_file::Elaborate(char const*, char const*, Map const*) 0x218 (synth_vrfx2)
0x3b9fd6: new_verific::VRFX2_EXTRACTOR::extract_hierarchy(char const*, BASEX_ELABORATE_INFO*, bool, bool) 0x3ac (synth_vrfx2)
One possible workaround is to use explicit port connection in your SystemVerilog design file. For example, replace (.invalidport) with (.invalidport(invalidport)).
This problem is scheduled to be fixed in a future release of the Quartus Prime software.