In the Intel® Quartus® Prime Pro Edition Software version 20.3, you may see the errors below when compiling the Intel Agilex® FPGA PHYLite IP.
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175001): The Fitter cannot place 1 pin, which is within ed_synth ed_synth.
Error(16234): No legal location could be found out of 1772 considered location(s). Reasons why each location could not be used are summarized below:
Error(175005): Could not find a location with: DQS_x36 (1 location affected)
Error(175008): Location was not in the legal region (1771 locations affected)
These errors are due to a hardware limitation. A configuration of the Intel Agilex FPGA PHYLite IP, where X8/X9 and X32/X36 DQS goups are used simultaneously in the same IO48 sub-bank, is unsupported.
