Article ID: 000076535 Content Type: Troubleshooting Last Reviewed: 06/19/2020

Why does the Intel® P-Tile Avalon® Memory Mapped IP for PCI Express* Gen4x4 Root Port Example Design error during compilation?

Environment

  • Intel® Stratix® 10 DX FPGA
  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
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    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.1 or earlier, the Intel® P-Tile Avalon® Memory Mapped IP for PCI Express* Gen4x4 Root Port Example Design reports error during compilation.

    Error(21410): Verilog HDL error at s10_rp_avmm_master_hwtcl.v(130): event control statement inside subprogram is not supported for synthesis

    Resolution

    To work around this, it is necessary to generate the simulation and synthesis file separately and re-compile the examaple design.

    This problem is scheduled to be addressed in a future release of the Intel® Quartus® Prime Pro Edition Software.

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