You may get this warning during Quartus® II software Analysis and Synthesis when synthesizing a Finite State Machine (FSM). This is an invalid warning displayed by the Quartus II software version 6.0 SP1. The incorrect warning message is not displayed beginning with the Quartus II software version 6.1.
This warning occurs when you assign the state variable for an inferred FSM to an output port. In the following example, arbiter_state is an output of size [1:0], and mystate is the assigned value, and it is used in a case statement of 4 possible options:
assign arbiter_state = mystate;
case (mystate)
...Branch 1...
...Branch 2...
...Branch 3...
...Branch 4...endcase
When Quartus II Analysis and Synthesis infers an FSM, it encodes the state variable using one-hot encoding. In this case, mystate has 4 states and thus has 4 bits. In this example, when you assign mystate to the signal called arbiter_state, the software encodes the state variable mystate before implementing the assignment. However, the software checks for bit truncation before encoding the value rather than after. Thus, the software interprets the right hand side of the assignment as 4 bits rather than 2, and issues the warning message. The truncation warning has no impact on the design functionality.
To eliminate the warning message in the Quartus II software version 6.0 and earlier, you can change the size of the target output signal (arbiter_state in the above example) to 4 bits and use just the lower two, least signficant, bits.