Description
No, the Arria® 10 PHYLite and the Stratix® 10 PHYLite IPs can't support two x4 DQ/DQS groups in one I/O lane. Each x4 DQ/DQS group must be placed in separate I/O lanes.
Resolution
Environment
Intel® Quartus® Prime Pro Edition
PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP
PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT