Article ID: 000076497 Content Type: Troubleshooting Last Reviewed: 01/18/2017

Why are the rx_latency_adj and tx_latency_adj status signals for the 1588 enabled 1G/2.5G/5G/10G Multi-rate Ethernet PHY not stable upon reset?

Environment

  • Arria® V GX FPGA
  • Arria® V SX SoC FPGA
  • Arria® V GT FPGA
  • Arria® V ST SoC FPGA
  • Arria® V GZ FPGA
  • Stratix® V GX FPGA
  • Stratix® V GT FPGA
  • Intel® Arria® 10 GT FPGA
  • Intel® Arria® 10 GX FPGA
  • Intel® Arria® 10 SX SoC FPGA
  • Intel® Quartus® Prime Pro Edition
  • 1G 2.5G 5G 10G Multi-rate Ethernet PHY Intel® FPGA IP
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    Description

    Due to the IP behavior, you may observe rx_latency_adj and tx_latency_adj value changing for a certain amount of iterations before they settle to fixed value.

    Resolution

    No workaround is required. This is an expected behavior. The valid latency value is the fixed value after certain amount if iterations. The latency value changes after reset as it is statistically calculated, hence require certain amount of iterations before it settles to a fixed value.

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