Article ID: 000076491 Content Type: Troubleshooting Last Reviewed: 04/22/2020

Why do I see incorrect audio frequency output from the HDMI Intel® FPGA IP RX core when fixed rate link(FRL) mode is enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
  • HDMI Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a problem with the HDMI Intel® FPGA IP RX core, audio output is broken when FRL mode is enabled.

    The internal audio clock is incorrectly recovered from the link clock based on the received number of pixels per clock(N) and CTS values in FRL mode.

    The audio works correctly in Transition Minimized Differential Signaling(TMDS) mode. 

    Resolution

    There is no work around for this problem in FRL mode. If possible use TMDS mode.
    This problem has been fixed in the Intel® Quartus® Prime Pro Edition software versions 20.1.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs