altera_fp_functions compare function generates top level file without required port

When you create compare functions for the floating-point IP cores in the 13.1 Quartus® II software release, the top-level .vhd file is generated without the required "b" port. This .vhd file error only occurs when creating compare functions; other functions from altera_fp_functions are not affected.

This issue is fixed in the 14.0 Quartus II software release.

In the 13.1 Quartus II software release, when you create a compare function called cmp, the software generates a top level file called cmp.vhd; this file is missing the required "b" port. You can modify cmp.vhd as follows to include required "b" port:

entity cmp is

port (

clk : in std_logic := \'0\'; -- clk.clk

areset : in std_logic := \'0\'; -- areset.reset

a : in std_logic_vector(31 downto 0) := (others => \'0\'); -- a.a

b : in std_logic_vector(31 downto 0) := (others => \'0\'); -- b.b

q : out std_logic_vector(0 downto 0) -- q.q

);

end entity cmp;

architecture rtl of cmp is

component cmp_0002 is

port (

clk : in std_logic := \'X\'; -- clk

areset : in std_logic := \'X\'; -- reset

a : in std_logic_vector(31 downto 0) := (others => \'X\'); -- a

b : in std_logic_vector(31 downto 0) := (others => \'X\'); -- b

q : out std_logic_vector(0 downto 0) -- q

);

end component cmp_0002;

begin

cmp_inst: component cmp_0002

port map(

clk => clk, -- clk.clk

areset => areset, -- areset.reset

a => a, -- a.a

b => b, -- b.b

q => q -- q.q

);end architecture rtl; -- of cmp