Article ID: 000076453 Content Type: Troubleshooting Last Reviewed: 04/18/2023

Why is my Intel® Arria® 10 FPGA DDR4 design failing compilation in the fitter when I choose "Automatically select a location" for ALERT# pin placement?


  • Intel® Quartus® Prime Standard Edition
  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Lite Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP

    If the "Automatically select a location" option is chosen in the Memory Topology/ Topology tab of the Intel® Arria® 10 FPGA DDR4 IP Editor, the IP will automatically choose a pin assignment for the mem_alert_n signal. If this option is selected and conflicting location constraints are applied to the mem_alert_n pin, fitter errors will result during compilation.

    The fitter errors will include these messages:

    Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s)).

    Error (15307): Cannot apply project assignments to the design due to illegal or conflicting assignments. Refer to the other messages for corrective action.


    If you use the "Automatically select a location" option, remove all location assignments and constraints for the mem_alert_n signal in your .QSF file. Intel recommends manually placing the mem_alert_n signal in the address/command bank for optimum timing margins by choosing the "I/O Lane with Address/Command Pins" option.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs