Article ID: 000076424 Content Type: Troubleshooting Last Reviewed: 01/09/2020

Why does the Low Latency 100-Gbps Ethernet IP Core with CAUI-4 PCS and RS-FEC enabled generate periodic blocks of errors after 2 hours when implemented in the Intel® Arria® 10 GT device?

Environment

  • Intel® Arria® 10 GT FPGA
  • Intel® Quartus® Prime Pro Edition
  • Low Latency 100G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime software versions 19.3 and earlier, the Low Latency 100-Gbps Ethernet IP Core with CAUI-4 PCS and RS-FEC enabled will generate periodic bursts of errors over time when implemented in the Intel® Arria® 10 GT device.

    Resolution

    To work around this issue, re-generate the IP core in the Intel® Quartus® Prime software 19.4 or later.

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.