Article ID: 000076422 Content Type: Error Messages Last Reviewed: 05/20/2020

Error: VHDL error at auk_dspip_roundsat_hpfir.vhd(103): value "4294967295" is outside the target constraint range (-2147483848 to 2147483647)

Environment

    Intel® Quartus® Prime Pro Edition
    FIR II Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.2, the error above can be seen when the output width of the FIR II Intel® FPGA IP is greater than or equal to 32 bits in rounding mode.

Resolution

To work around this error in existing software, set the IP parameter "Output LSB Rounding" to "Truncation", or still use "Rounding", but ensure that the output width is smaller than 32 bits.

This problem has been fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.1.

Related Products

This article applies to 4 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs
Intel® Cyclone® 10 FPGAs
Intel Agilex® 7 FPGAs and SoC FPGAs

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