Article ID: 000076417 Content Type: Troubleshooting Last Reviewed: 10/12/2020

Why is the Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express* GUI showing incorrect data bus width and clock frequency?

Environment

  • Intel® Agilex™ F-Series FPGAs and SoC FPGAs
  • Intel® Stratix® 10 DX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
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    Description

    Due to a problem in the Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express* for the Intel® Quartus® Prime Pro Edition software version 20.2, the GUI will show incorrect data bus width and clock frequency. 

    Resolution

    The Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express* User Guide, Table PHY Clock and Application Clock Frequencies, lists the correct values of data widths and application clock frequency (p_app_clk) for the Intel® FPGA P-Tile Avalon® Memory-mapped IP for PCI Express*.

    https://www.intel.com/content/www/us/en/programmable/documentation/aib1557867923977.html#rsc1567029023459

     

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.

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