Article ID: 000076416 Content Type: Troubleshooting Last Reviewed: 01/09/2020

Why does the example design testbench for the single channel E-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP 10GBASE-KR variant not complete in either Ncsim® or Xcellium®?

Environment

  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Agilex™ FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro software version 19.4, the example design testbench for  E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP variant with a single channel of 10GBASE-KR selected will not complete when using Ncsim® or Xcellium®. 

    Resolution

    To work around this issue, increase the number of channels in your 10GBASE-KR variant to greater than ‘1’ when simulating the example design with Ncsim or Xcellium.

    This problem is fixed starting with the Intel® Quartus® Prime Pro software version 20.1.

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