Article ID: 000076414 Content Type: Troubleshooting Last Reviewed: 05/05/2021

Why does the Intel® Stratix® 10 PCIe* Avalon® -MM Hard IP fail to respond to inbound memory read TLPs with the Relaxed Ordering bit set?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a limitation of the Intel® Stratix® 10 PCIe* Avalon® -MM Bridge, inbound memory read TLPs with the Relaxed Ordering bit set will be dropped and no completion returned , which can cause system failure.

    Resolution

    To work around this problem, constrain the link partner to only send the Memory read TLPs without the Relaxed Ordering bit set to the Intel® Stratix® 10 PCIe* Avalon® -MM Hard IP.

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