Article ID: 000076390 Content Type: Troubleshooting Last Reviewed: 08/25/2023

Why is the Intel® Arria® 10 PHYLite IP core interface_locked signal not asserted?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® Quartus® Prime Standard Edition
  • PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Due to a known limitation in the Intel® Arria® 10 PHYLite IP, the interface_locked signal will not assert when all odd-numbered index pins in an I/O lane are unused as data pins. However, the Intel® Arria® 10 PHYLite IP is fully functional for data transfers.

    Resolution

    To work around this problem, use at least one odd-numbered index pin in an I/O lane (such as pin_index 1, 3, 5 … 11) for the data pins in your Intel® Arria® 10 PHYLite design.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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