Article ID: 000076385 Content Type: Product Information & Documentation Last Reviewed: 02/15/2023

How can the Intel® Stratix®10 MX HBM2 controller efficiency be improved?


  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP

    The Intel® Stratix®10 MX FPGAs integrate 3D stacked HBM2 DRAM memory, including the HBM2 hard memory controller. Therefore, maximizing the HBM2 memory controller efficiency is very important. 




    Several factors can affect controller efficiency. For best efficiency, you should consider these factors in your design:

    • User-interface frequency vs HBM2 interface frequency - The frequency of user logic in the FPGA fabric plays an important role in determining HBM2 memory efficiency.

    • Controller Settings:

    • Disable the Reorder Buffer in the Controller Settings to achieve improved efficiency. (However, if the application requires that read data be provided in the same order as the read requests, then it is preferable to Enable the Reorder Buffer.)
    • Burst length - The pseudo-BL8 mode helps to ensure shorter memory access timing between successive BL4 transactions, to improve controller efficiency.

    • Traffic Patterns - Traffic patterns play an important role in determining controller efficiency.

    • Sequential vs random DRAM addresses: Sequential addresses enable the controller to issue consecutive write requests to an open page and help to achieve high controller efficiency. Random addresses require constant PRECHARGE/ACTIVATE commands and can reduce controller efficiency.
    • Set the User Auto Precharge Policy to FORCED and set the awuser/aruser signal on the AXI interface to HIGH to enable Auto Precharge for random transactions. For sequential transactions, set the Auto Precharge Policy to HINT.
    • Sequential Read only or Write Only transactions: Sequential read-only or write-only transactions see higher efficiency as they avoid bus turnaround times of the DRAM bi-directional data bus.

    • AXI Transaction IDs - Use of different AXI transaction IDs helps the HBM2 controller schedule the transactions for high efficiency. Use of the same AXI transaction ID preserves command order and may result in lower efficiency.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 MX FPGA