The MAX® 10 ADC IP offers a fixed sampling rate of 1Msa/s for total sampling points.
You can lower the sampling rate to give a larger settling time margin for the filter design, by following the workaround below.
You can lower the sampling rate of the ADC IP by selecting a higher clock frequency in the ADC IP GUI than the frequency that is set for the PLL output clock that drives it.
For example, when the PLL is configured to provide a 10MHz clock to the ADC IP, you are supposed to set the reference clock in the ADC IP to 10MHz to get 1Msa/s sampling rate.
However, if you set the reference clock to 20MHz, the sampling rate will reduce by half which in this case is 500ksa/s.