When targetting Intel® Arria® 10 and Intel® Stratix® V FPGAs, the Intel® Low Latency 40- and100-Gbps Ethernet IP cores support a minimum frame size of 64 bytes as required by the IEEE specifications.
Due to the design of the Intel® 40- and 100-Gbps Ethernet IP cores, the IP cores may hang and/or behave unexpectedly for RX frames less than 64 bytes in length.
To work around this problem the far end transmitter must adhere to the required minimum packet size of 64 bytes.
This problem is not scheduled to be fixed in any future Quartus® Prime software release.
Intel® Stratix® 10 FPGAs do not have this limitation.