Article ID: 000076352 Content Type: Troubleshooting Last Reviewed: 11/28/2023

Why does the FIR II Intel® FPGA IP use fewer DSP Blocks than the number shown in the resource estimation section of the IP GUI?

Environment

    Intel® Quartus® Prime Pro Edition
    Intel® Quartus® Prime Standard Edition
    FIR II Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The string "Number of DSPs" under Resource Estimation in the FIR II Intel® FPGA IP GUI is inaccurate. It should be the "Number of 18 x 18 multipliers". 

This results in the Intel® Quartus® Prime Pro Edition Software Fitter reporting fewer DSP Blocks used than the estimation. 

 

 

Resolution

No workaround is needed.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

Related Products

This article applies to 1 products

Intel® Programmable Devices

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