Article ID: 000076351 Content Type: Troubleshooting Last Reviewed: 05/05/2021

When using Windows* why does the Intel® FPGA P-Tile Avalon® Memory Mapped IP for PCI* Express  Example Design fail to generate?

Environment

    Intel® Quartus® Prime Pro Edition
    Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
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Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software Windows* version 20.1, the Intel® FPGA P-Tile Avalon® Memory Mapped IP for PCI Express* Example Design will fail to generate in Gen4x4 Root Port mode.

Resolution

The example design can be generated correctly by the Linux* version of the Intel® Quartus® Prime Pro Edition software version 20.1.

This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 20.4.

Related Products

This article applies to 5 products

Intel® Stratix® 10 GX FPGA
Intel® Stratix® 10 MX FPGA
Intel® Stratix® 10 DX FPGA
Intel® Stratix® 10 TX FPGA
Intel® Stratix® 10 SX SoC FPGA

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