Article ID: 000076350 Content Type: Troubleshooting Last Reviewed: 09/28/2020

Why does the reset_status signal not respond when the npor signal is deasserted in the Avalon®-ST Intel® Stratix® 10 Hard IP for PCI* Express?

Environment

  • Intel® Stratix® 10 GX FPGA
  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 SX SoC FPGA
  • Intel® Quartus® Prime Pro Edition
  • Avalon-ST Intel® Stratix® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    Due to a problem with the Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express IP in the Intel® Quartus® Prime Pro Edition software version 19.2 and earlier, you may encounter the above problem.

    Resolution

    This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition software version 19.3.

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