Why does my reset signal get inverted when using incremental compilation?

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may see incorrect behavior of reset signals when using incremental compilation. Specifically, the operation of the reset may be the inverse of what it is expected. This problem can occur if all of the following are true in your design:

• An active-low reset is generated from a register in a design partition, including the top-level partition
• The reset is inverted and connected to a lower-level partition
• The reset is used an active-high asynchronous reset within the lower-level partition
• The reset is promoted to a global or regional clock buffer
• The lower-level partition preserves previous synthesis or fitting results, and the upper-level partition is compiled from source

To avoid this problem, ensure your design does one of the following:

• Use the same sense (active-high or active-low) reset throughout your design
• Invert the reset within the lower-level partition where it is used instead of in the upper-level partition
• Avoid the use of global or regional clock routing for the reset signal
• Use the same preservation level for both the upper-level and lower-level partitions
• Turn off incremental compilation

This problem is scheduled to be fixed in a future release of the Quartus II software.