Article ID: 000076309 Content Type: Troubleshooting Last Reviewed: 01/21/2020

Why do I see warnings when using the 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and LVDS I/O or 1000BASE-X/SGMII PCS and LVDS I/O is selected in the Intel® Agilex® Triple-Speed Ethernet Intel® FPGA IP ?

Environment

  • Intel® Agilex™ FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Software Edition version 19.4, the warnings shown will be seen when selecting the 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and LVDS I/O or the 1000BASE-X/SGMII PCS and LVDS I/O option is selected in the Intel® Agilex® Triple-Speed Ethernet Intel® FPGA IP core.

    Warning: test.eth_tse_0.i_lvdsio_terminator_0.pll_areset_iopll: Associated reset sinks not declared

    Warning: test.eth_tse_0.iopll: Able to implement PLL - Actual VCO frequency differs from requested setting

    Warning: test.eth_tse_0.ref_clk_module.out_clk/iopll.refclk: iopll.refclk requires 125000000Hz, but source has frequency of 0Hz

    Resolution

    These warnings can be safely ignored as functionality is not impacted when using the Intel® Agilex® Triple-Speed Ethernet Intel® FPGA IP core.

     

     

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.