Article ID: 000076300 Content Type: Troubleshooting Last Reviewed: 11/03/2016

Why is the PAGE_RECEIVE bit of 1G/2.5G/10G Multi-rate Ethernet PHY IP Core not cleared in 1G/2.5G mode?

Environment

    Intel® Quartus® Prime Pro Edition
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Description Due to a problem in the Arria® V 1G/2.5G/10G Multi-rate Ethernet PHY IP Core, the PAGE_RECEIVE bit at address 0x06[1] may not be automatically cleared once it is read in 1G/2.5G mode. This is a known problem in the Quartus® Prime® version 15.1.2
Resolution This problem will be fixed in version 16.1 of the Quartus Prime software.

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