Article ID: 000076296 Content Type: Troubleshooting Last Reviewed: 11/14/2017

What is the minimum pulse width required for the Arria 10 EMIF IP global_reset_n signal ?

Environment

Bug ID: FB: 480925;

Quartus Edition

Intel® Quartus® Prime Pro Edition

Version Found: 16.0

FPGA Intellectual Property

External Memory Interfaces Intel® Arria® 10 FPGA IP

Version Found: 16.0

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Description

The minimum reset pulse width requirement is 100ns.

Description

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