Article ID: 000076296 Content Type: Troubleshooting Last Reviewed: 11/14/2017

What is the minimum pulse width required for the Arria 10 EMIF IP global_reset_n signal ?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Arria® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The minimum reset pulse width requirement is 100ns.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs