Article ID: 000076255 Content Type: Troubleshooting Last Reviewed: 02/15/2023

Why does the Frame Buffer II (4K Ready) Intel® FPGA IP drop my ancillary (user) packets?

Environment

    Intel® Quartus® Prime Pro Edition
    Frame Buffer II (4K Ready) Intel® FPGA IP
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Description

Due to a problem with the Frame Buffer II (4K Ready) Intel® FPGA IP when Module is Frame Writer only  is selected, you cannot change the Maximum ancillary packets field.  That field, under the Memory section of the parameter editor, will be greyed out and not editable.

Frame buffer in frame writer mode, default Ancillary packets = 0

This field defaults to 0 (zero), which will cause all ancillary packets (also known as User packets) to be dropped.

Resolution

To work around this problem, de-select Module is Frame Writer only, change the Maximum ancillary packets per frame to your desired setting, then re-select Module is Frame Writer only.

Frame buffer with frame writer mode off and Ancillary packets entered

Frame buffer in frame writer mode, note Ancillary packets = 3

This problem is fixed in the Intel® Quartus® Prime Software version 18.0.

Related Products

This article applies to 9 products

Intel® Arria® 10 FPGAs and SoC FPGAs
Intel® Cyclone® 10 FPGAs
Intel® MAX® 10 FPGAs
Arria® II FPGAs
Arria® V FPGAs and SoC FPGAs
Cyclone® IV FPGAs
Cyclone® V FPGAs and SoC FPGAs
Stratix® IV FPGAs
Stratix® V FPGAs

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