Article ID: 000076252 Content Type: Troubleshooting Last Reviewed: 10/30/2024

Why is the waitresponsevalid signal not exported when using the Avalon®-MM Pipeline Bridge FPGA IP when “Use Avalon Transaction Responses” option is enabled?

Environment

    Intel® Quartus® Prime Lite Edition
    Intel® Quartus® Prime Pro Edition
    Intel® Quartus® Prime Standard Edition
    Memory Mapped
    Avalon-MM Pipeline Bridge Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Avalon®-MM Pipeline Bridge FPGA IP, when “Use Avalon Transaction Responses” option enabled, only writeresponse signal is exported, writeresponsevalid is not.

For connections between Avalon-MM masters and Avalon-MM Pipeline Bridge, where write responses are expected by masters, the absence of writeresponsevalid signal will result in potential issues.

Resolution

This problem has been fixed in Intel® Quartus® Prime Pro Edition software version 20.3 and later versions.

Related Products

This article applies to 1 products

Intel® Programmable Devices

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.