Article ID: 000076250 Content Type: Troubleshooting Last Reviewed: 07/15/2020

Why does the PCIe* DMA Controller Intel® Stratix® 10 FPGA IP send two continuous MSI interrupts for the DMA operation?

Environment

  • Intel® Stratix® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Avalon-MM Intel® Stratix® 10 Hard IP for PCI Express
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    Critical Issue

    Description

    Due a problem in the PCIe* DMA Controller Intel® Stratix® 10 FPGA IP, the DMA controller will send out two continuous MSI interrupts, one if for the DMA Read MSI vector and the other is for the DMA Write MSI vector.

    When either a DMA Read or DMA Write operation completes, if the driver programs the “Write Data Mover Interrupt Control Register”(MSI Address and Vector For DMA Write) and the “Read Data Mover interrupt control register” (MSI Address and Vector For DMA Read), both interrupts will be sent.

    Resolution

    To work around this problem, please use the alternative method to send the MSI interrupts by programing the last descriptor of the DMA read or DMA write operation as the MSI Address and MSI Vector.

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