Article ID: 000076249 Content Type: Troubleshooting Last Reviewed: 02/03/2020

When using the Low Latency Ethernet 10G MAC Intel® FPGA IP, why does changing the value of the rx_transfer_control register disable the datapath instantly and not at the packet boundary?

Environment

    Intel® Quartus® Prime Pro Edition
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Critical Issue

Description

Due to a problem with the Intel® Quartus® Prime Pro software version 19.2 and earlier, the Low Latency Ethernet 10G MAC Intel® FPGA IP with 1G or 2.5G speed, the RX path is enable or disabled immediately as the change of value in rx_transfer_control register. 

The following are the affected speed parameters:


1. 1G/2.5G
2. 1G/2.5G/10G

Resolution

This problem has been fixed starting in the Intel® Quartus® Prime Pro software version 19.3.

Related Products

This article applies to 4 products

Intel® Cyclone® 10 GX FPGA
Intel® Arria® 10 FPGAs and SoC FPGAs
Stratix® V FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs

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