Article ID: 000076246 Content Type: Troubleshooting Last Reviewed: 09/23/2020

<your_ip>.regmap file not generated when using the Stratix® 10 E-Tile Hard IP for Ethernet Intel® FPGA IP and E-Tile CPRI PHY IP Core is generated?

Environment

  • Intel® Stratix® 10 MX FPGA
  • Intel® Stratix® 10 TX FPGA
  • Intel® Stratix® 10 DX FPGA
  • Intel® Quartus® Prime Pro Edition
  • Ethernet
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    UG-20160 | 2020.06.29 and earlier versions indicate that the file <your_ip>.regmap will be created when generating the Stratix® 10 E-Tile Hard IP for Ethernet Intel® FPGA IP and E-Tile CPRI PHY IP Core. This is incorrect. The file <your_ip>.regmap is not generated.

    Resolution

    This mistake has been removed from the IP Core Generated Files table, updated for version 20.2 of the Intel® Quartus® Prime Design Suite.

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