Article ID: 000076182 Content Type: Troubleshooting Last Reviewed: 02/09/2015

Why do I get a Fatal Error when I compile a design using an EDIF source file?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in the Quartus® II software version 14.1 and later, you may get a Fatal Error when compiling an EDIF netlist.
    Resolution

    To work around this problem, generate a Verilog Quartus Mapping file (.vqm) from your 3rd party synthesis tool instead.

    The problem is scheduled to be fixed in a future release of the Quartus II software.

    Related Products

    This article applies to 1 products

    Intel® Programmable Devices

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