Article ID: 000076176 Content Type: Troubleshooting Last Reviewed: 02/08/2013

Compilation error in Arria V post-fit simulation using Aldec Active-HDL 9.1

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    If your design targets an Arria V or an Arria V GZ device and you perform a post-fit simulation in version 12.1 of the Quartus II software using the Aldec Active-HDL 9.1 EDA simulator, a compilation error might occur.

    Resolution

    Upgrade to Aldec Active-HDL version 9.2.

    Related Products

    This article applies to 2 products

    Arria® V GZ FPGA
    Arria® V FPGAs and SoC FPGAs

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.