Article ID: 000076176 Content Type: Troubleshooting Last Reviewed: 02/08/2013

Compilation error in Arria V post-fit simulation using Aldec Active-HDL 9.1

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

If your design targets an Arria V or an Arria V GZ device and you perform a post-fit simulation in version 12.1 of the Quartus II software using the Aldec Active-HDL 9.1 EDA simulator, a compilation error might occur.

Resolution

Upgrade to Aldec Active-HDL version 9.2.

Related Products

This article applies to 2 products

Arria® V GZ FPGA
Arria® V FPGAs and SoC FPGAs

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