GXB 0 ppm Warning for SerialLite II Designs with Custom PHY

The Quartus II software will show the following warning for designs that use more than 1 channel between the SerialLite II IP core and the Custom PHY IP during integration:

Critical Warning (21196): Coreclk source from HSSI 8G RX PCS atom slite2_x4_2g_5agx_cusphy:u_slite2_x4_2g_5agx_cusphy|altera_xcvr_custom: slite2_x4_2g_5agx_cusphy_inst|av_xcvr_custom_nr:A5|av_xcvr_custom_native: transceiver_core|av_xcvr_native:gen.av_xcvr_native_insts[3].gen_bonded_group. av_xcvr_native_inst|av_pcs:inst_av_pcs|av_pcs_ch:ch[0].inst_av_pcs_ch| av_hssi_8g_rx_pcs_rbc:inst_av_hssi_8g_rx_pcs|wys does not have the same 0 ppm source with respect to PCS internal clock because of coreclk input of the Receiver channel is not driven by its own rx clkout.

You can safely ignore this warning if your design targets Arria V or Stratix V devices.

This issue will be fixed in a future version of the SerialLite II IP core.