Article ID: 000076157 Content Type: Product Information & Documentation Last Reviewed: 11/13/2013

How do I set the paramter FAST_SIMULATION of my 40- and 100-Gbps Ethernet MAC and PHY in VHDL?


  • Quartus® II Subscription Edition

    In Quartus® II software version v13.0SP1 and earlier you must manually modify the IP libraries of the 40- and 100-Gbps Ethernet MAC and PHY IP Core to set the parameter FAST_SIMULATION if you generated the IP Core in VHDL.

    This parameter reduces the time for the lanes to be deskewed in simulation.


    Follow the procedure below to add the parameter FAST_SIMULATION to your IP libralies.

     1. Open ./gen_100_sim/alt_e100_phy/alt_e100_phy_0001.vhd for 100G PHY or ./gen_40_sim/alt_e40_phy/alt_e40_phy_0001.vhd for 40G PHY with a text editor
     2. Add the parameter into the component declaration of the alt_e100_phy_pcs or alt_e40_phy_pcs. Below is an example for the 100G PHY.

     component alt_e100_phy_pcs is
      generic (
       DEVICE_FAMILY  : string  := "Stratix V";
       VARIANT        : integer := 3;
       STATUS_CLK_KHZ : integer := 100000;
       FAST_SIMULATION : integer := 1

     3. Add the parameter to the phy_pcs instance. Below is an example for the 100G PHY.

     phy_pcs : component alt_e100_phy_pcs
      generic map (
       DEVICE_FAMILY  => "Stratix V",
       VARIANT        => 3,
       STATUS_CLK_KHZ => 100000,
       FAST_SIMULATION  => 1

    Starting from Quartus II Software version v13.1, this parameter is available in the top-level entity of the IP, and no manual modification of the libraries is required.

    Related Products

    This article applies to 4 products

    Arria® V GZ FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Stratix® V GX FPGA



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