Article ID: 000076153 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is it possible to share one clock pin with two or more altpll instances?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

It may or may not be possible to share one clock pin with two or more altpll instances, it depends on the device family you are using.

Refer to the Supported PLL Drivers section in Table 1 of PLL Clock Management Features in Altera FPGAs.

Related Products

This article applies to 1 products

Stratix® III FPGAs