Article ID: 000076120 Content Type: Error Messages Last Reviewed: 09/11/2012

Internal Error: Sub-system: VPR20K, File: ygr_arch/ygr_route_timing.c, Line: 5244


Description This error may occur in the Quartus® II software version 2.2 when you attempt to use the SigntalTap® II embedded logic analyzer or the SignalProbe feature to monitor the DQS pin in a double-date rate (DDR) block.

All fanouts of the DQS pin must be clocks feeding I/O input registers or DDIO input registers. The DQS signal cannot be monitored because monitoring a signal requires that the signal fan out to a logic element (LE). This is documented in the following Solution: Can I use the SignalTap II embedded logic analyzer to monitor the DQS signals in my double data rate (DDR) block?

This has been addressed in Quartus II software version 3.0 by removing the DQS signals from the SignalTap II/SignalProbe filter.

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Stratix® FPGAs