Article ID: 000076093 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is there an issue with “Skip memory initialization” option in UniPHY based DDR2 SDRAM and DDR3 SDRAM Controller?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes, in the 11.0 version of the IP, Skip memory initialization option does not skip the initialization process. UniPHY based DDR2 SDRAM and DDR3 SDRAM controller does not support skipping memory initialization option.

 

Although the IP does not skip initialization in the simulation, when this option is turned on, required delays between specific memory initialization commands are skipped to speed up simulation so it does help speed up the simulation.

 

The IP GUI will be fixed to reflect the true function of this option in the future version.

 

Related Products

This article applies to 8 products

Stratix® III FPGAs
Stratix® V GS FPGA
Stratix® IV E FPGA
Stratix® V E FPGA
Stratix® V GX FPGA
Stratix® V GT FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA