Why does the TimeQuest timing analyzer generate recovery and removal violations for the DCFIFO megafunction?

In the Quartus II software version 11.0 SP1 and earlier, the TimeQuest timing analyzer way generate recovery and removal violation in the read-clock domain of the DCFIFO megafunction if you turn on Add circuit to synchronize ‘aclr’ with ‘wrclk’ option.

To avoid these violations, declare paths through the aclr pin as false paths. These false path declarations are valid because the registers in the read-clock domain are guaranteed not to toggle after aclr de-assertion, because the queue is empty.

These paths are scheduled to be automatically declared as false paths in a future version of the Quartus II software.