Article ID: 000076075 Content Type: Product Information & Documentation Last Reviewed: 05/19/2015

How do I enable CRC error injection when using the SerialLite III IP?



The Altera® SerialLite III IP MegaCore® (SLIII) function allows you to inject CRC errors, which can be useful when verifying the PHY layer operation during debugging or board bringup phase. To enable the CRC error injection, reconfigure the transmitter PHY using a reconfiguration controller. When enabled, your application can force CRC errors by asserting the error injection control signal on the SerialLite III instance.


1. Add a JTAG-to-Avalon® Master Bridge to your Qsys system. This is required to drive the reconfiguration controller to enable the CRC error enable bit in the respective transceiver channels.

2. Compile the design.

3. Obtain the logical channel number for the SLIII transceiver channels from the Quartus® II fitter report. The logical channel assignment can be found by clicking \'Resource Section -> GXB Reports -> Transceiver Reconfiguration Report\'

4. Edit the attached tcl file SOURCE_RECONFIG_BASE value to match the base address for the reconfiguration controller in your Qsys system.


5. Launch System Console from the Quartus Tools menu. Use the source command to open the attached Tcl file in System Console to enable CRC error injection as shown below:

    a. source crc_err_enable.tcl

    b. example command use (see the Tcl file for details)

        - crc_err_enable 0 1 (enables logical channel 0 CRC error injection)

        - crc_err_enable {0 1 2} 1 (enables logical channel 0,1,2 CRC error injection)

        - crc_err_enable {0 1 2} 0 (disables logical channel 0,1,2 CRC error injection) 

6. Assert SerialLite III Source crc_error_inject input to 1. (Alternatively, you can tie the crc_error_inject to 1 and just use the Tcl command to enable/disable the error injection)

7. Monitor the CRC error status, error[N-1:0] (error_rx[N-1:0] for duplex core) signals, at the SerialLite III IP receiver. (N = number of lanes)

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