Article ID: 000076039 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Why cant I use a transceiver recovered clock to feed a transmitter PLL reference clock on Altera transceiver devices?


  • Stratix® II GX FPGA
  • Stratix® IV GX FPGA
  • Stratix® IV GT FPGA
  • Arria® II GX FPGA
  • Arria® II GZ FPGA
  • Stratix® V GX FPGA
  • Stratix® V GT FPGA
  • Stratix® V GS FPGA
  • Arria® V GX FPGA
  • Arria® V GT FPGA

The Quartus® II Software will deliberately prevent you from connecting a recovered clock from a receiver to the reference clock input of a transmitter PLL.

The recovered clock is extracted from the clock embedded in the received datastream. As the datastream has propagated across a channel, the recovered clock will have undefined jitter characteristics which if fed into the reference clock of a transmitter PLL, may cause the transmit jitter to exceed a given protocols' transmit jitter specification.

The recommended method of implementing a recovered clock synchronous architecture is to route the recovered clock outside of the FPGA, and to pass the clock through a jitter cleaner before routing back onto the FPGA through one of the dedicated transceiver reference clock pins.



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