The design might fail compilation and receive the following error if turn on the "Enable TX PLL select for 1/1.000 and 1/1.001 data rate reconfiguration" for SDI dual link.
Error (167085): Atom "<name of IP>:inst|sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|rc_s4gxb_tx_2pll:gen_tx_alt4gxb_2pll.u_gxb|alt4gxb:alt4gxb_component|alt4gxb_0i67:auto_generated|tx_pll0" of type "GXB PLL" can only be clocked from one of the following core signals
Info (167001): I/O input buffer atom "tx_serial_refclk~input"
Info (167001): I/O input buffer atom "tx_serial_refclk1~input"
This issue only happens in Stratix® IV and Arria® II devices if the IO_STANDARD of tx_serial_refclk & tx_serial_refclk1 are not defined properly.
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to tx_serial_refclk1
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to tx_serial_refclk
Or
set_instance_assignment -name IO_STANDARD "LVDS" -to tx_serial_refclk1
set_instance_assignment -name IO_STANDARD "LVDS" -to tx_serial_refclk