Article ID: 000076014 Content Type: Troubleshooting Last Reviewed: 04/03/2023

Why does the DDR3 SDRAM Controller with UniPHY Intel® FPGA IP return invalid read data after the individual multi-port front end port is reset?

Environment

  • Quartus® II Subscription Edition
  • DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
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    Description

    Due to a problem in the Quartus® II software, the DDR3 SDRAM Controller with UniPHY Intel® FPGA IP might return invalid read data after an individual multi-port front end (MPFE) port is reset (mp_*reset_n*), without resetting the whole controller (ctl_reset_n/soft_reset_n/global_reset_n). This problem occurs because the write address register for the read data FIFO is not being reset together with the read address register. This mismatch leads to read addresses pointing to the wrong location of the read data returned by the controller.

    Resolution

    This problem is fixed in the Quartus® II software v15.0.

    Related Products

    This article applies to 11 products

    Cyclone® V GX FPGA
    Arria® V GZ FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Arria® V SX SoC FPGA

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