Article ID: 000076014 Content Type: Troubleshooting Last Reviewed: 12/26/2013

Why does the DDR3 hard memory controller with UniPHY return invalid read data after the individual multi-port front end port is reset?

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Description

Due to a problem in the Quartus® II software, the DDR3 hard memory controller with UniPHY may return invalid read data after an individual multi-port front end (MPFE) port is reset (mp_*reset_n*), without resetting the whole controller (ctl_reset_n/soft_reset_n/global_reset_n). This problem occurs because the write address register for the read data FIFO is not being reset together with the read address register. This mismatch leads to read addresses pointing to the wrong location of the read data returned by the controller.

Resolution This problem will be fixed in a future version of the Quartus II software.

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This article applies to 11 products

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