Article ID: 000075991 Content Type: Troubleshooting Last Reviewed: 09/02/2014

Are there any known problems with rxvalid occasionally deasserting when the Rate Match FIFO performs a SKP insert operation when using Gen3 soft PIPE on Stratix V GX devices?

Environment

  • Quartus® II Subscription Edition
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    Description

    Yes, there is a known problem in PCI Express Gen3 soft PIPE where rxvalid is occasionally deasserted when the Rate Match FIFO performs a SKP insertion on Stratix® V GX devices.

    This issue is seen in systems that do not use a common reference clock. No issues are seen when a common clock is used.

    Resolution

    To workaround this issue, ignore the rxvalid signal during SKP insertion and instead use rxstatus on the PIPE interface to know when a SKP character is inserted (rxstatus = 001). 

    Related Products

    This article applies to 3 products

    Stratix® V FPGAs
    Stratix® V GT FPGA
    Stratix® V GX FPGA

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