Description
Yes, there is a known problem in PCI Express Gen3 soft PIPE where rxvalid is occasionally deasserted when the Rate Match FIFO performs a SKP insertion on Stratix® V GX devices.
This issue is seen in systems that do not use a common reference clock. No issues are seen when a common clock is used.
Resolution
To workaround this issue, ignore the rxvalid signal during SKP insertion and instead use rxstatus on the PIPE interface to know when a SKP character is inserted (rxstatus = 001).